![]() Gupta GK, Jha SK (2021) Formation of fault and balanced ring for fault tolerance in Dmesh network. Wang C, Hu W-H, Lee SE, Bagherzadeh N (2011) Area and power-efficient innovative congestion-aware network-on-chip architecture. New Paradigms for VLSI Systems Design, ISVLSI In: Proceedings IEEE computer society annual symposium on VLSI. Kumar SA et al (2002) A network on chip architecture and design methodology. Kundu S, Chattopadhyay S (2014) Network-on-chip: the next generation of system-on-chip integration CRC Press. ![]() Thus, DiamondMesh establishes to be a highly efficient diagonal mesh-based topology for a variety of applications.īenini L, De Micheli G (2002) Networks on chips: a new SOC paradigm. The evaluation results show that there has been a significant reduction of latency compared to Mesh and other diagonal mesh topologies except DMesh and a considerable reduction of area and power compared to the DMesh topology. The proposed topology and other considered topologies have been synthesised using xilinx vivado design compiler and the results have been analysed. With the help of Booksim2.0 simulator, the proposed topology has been evaluated under a variety of traffic patterns and the results have been compared to those obtained with Mesh and the existing diagonal mesh topologies. Topological properties of DiamondMesh have been explored and compared with that of other competitive diagonal mesh topologies. By introducing diagonal links into the baseline mesh topology, the proposed DiamondMesh improves network performance while retaining the regular, simple and scalable properties of the Mesh topology. ![]() The present research work proposes an energy efficient diagonal mesh based topology called DiamondMesh.
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